Color image data or the like is image data formed of pixel data of N bits (N is an integer equal to or greater than two). As image processing on such image data, data conversion processing is widely performed for image quality improvement, expansion, reduction and the like. The image data is normally pixel value data acquired by scanning the image for every pixel line. As a method for realizing high-speed processing, pipeline processing (parallel processing) is used for the data conversion processing (image processing) on such image data. In this pipeline processing, many pipeline registers are used.
The pipeline register used for the image processing normally has a plurality of flip-flop circuits which are provided per bit of the image data. The plurality of flip-flop circuits are supplied with a common clock signal for their operation and hold the image data.
However, in the pipeline processing, as the content of the image processing becomes more complicated, the number of required flip-flop circuits increases. As a result, the power consumption in the switching operation of each flip-flop circuit increases. Especially, since portable electronic devices such as a digital camera and a portable information terminal are mainly battery-powered, it is desirable to perform image processing with as low power consumption as possible.
Therefore, in order to achieve an image processing circuit with low power consumption, applying the technology disclosed in PTL 1 to the flip-flop circuits of an image processing circuit is a possible solution.
The technology disclosed in PTL 1 (hereinafter “related art”) provides a synchronization register that receives, as input, higher order 8 bits of 16-bit input data. Moreover, the related art provides a synchronization register that receives, as input, lower-order 8 bits of the 16-bit input data. Further, the related art provides a comparison circuit and a clock gating control circuit for every synchronization register.
The comparison circuit determines whether the input value and output value (both are 8 bits) of the synchronization register are the same. When it is determined that the input value and the output value are the same, the clock gating control circuit controls the supply of a clock signal to the synchronization register. That is, the clock gating control circuit prevents the clock signal from being supplied to the synchronization register. Moreover, even in a case where the higher order 8 bits of input data are invalid, the clock gating control circuit for the higher order 8 bits stops the supply of the clock signal to the synchronization register for the higher order 8 bits.
In a case where the input value and output value of the synchronization register are the same, since the value to be held does not change, it can be said that the switching operation of the synchronization register is a useless operation. Therefore, such a related art can reduce the useless switching operation of the synchronization register. That is, the related art can reduce the power consumption of the synchronization register without impairing the function of the synchronization register.
In a case where the input value and output value of a flip-flop circuit in an image processing circuit are the same, it can be said that the switching operation is a useless operation. Therefore, applying the related art to each flip-flop circuit of the image processing circuit allows the image processing circuit to attempt a reduction in the power consumption.